The present invention relates to an amplification type solid-state image pickup device and a driving method therefor. More specifically, the invention relates to an amplification type solid-state image pickup device, as well as a driving method therefor, which includes a plurality of pixels each having a photoelectric conversion element and a transfer transistor for transferring signal charge of the photoelectric conversion element, where signals derived from the individual pixels are amplified and outputted to a signal line in common to the pixels.
Generally, there has been wide-spreading an amplification type solid-state image pickup device which has a pixel part provided with an amplification function and a scanning circuit disposed around the pixel section, where pixel data is read from the pixel section by the scanning circuit. In particular, there has been known an APS (Active Pixel Sensor) type image sensor formed of CMOS (Complementary Metal Oxide Semiconductor) which is advantageous for integration of the pixel part with peripheral drive circuit and signal processing circuit.
The APS type image sensor normally includes, in one pixel, a photoelectric conversion part, an amplification part, and a pixel selection part and a reset part. Therefore, for makeup of the APS type image sensor, normally, three to four MOS transistors (Tr) are used in addition to the photoelectric conversion part formed of photodiodes (PD).
Providing three to four MOS transistors per pixel as shown above would become a constraint on reduction of the pixel size. Therefore, lately, there has been proposed a technique for reducing the number of transistors per pixel as shown in FIG. 12 (see, e.g., JP H09-46596A).
The amplification type solid-state image pickup device shown in FIG. 12 includes a plurality of pixels each made up of a photodiode 101 and a transfer transistor 102, and further includes a charge detection node 108 common to a plurality of pixels arrayed in a column direction, a reset transistor 131, an amplification transistor 132 and a select transistor 133. Between a vertical signal line 135 and the ground is interposed a constant-current load transistor 134. All the transfer transistors 102, 131, 132 and 133 are n-channel transistors, and turned ON and OFF depending on High or Low of gate driving signals, respectively.
As shown in FIG. 13, in a period T1, a gate driving signal φR(m) to be applied to the reset transistor 131 goes High level, causing the potential under the gate to become deeper, where there occurs a charge move from the charge detection node 108 to the drain side of the reset transistor 131, causing the voltage of the charge detection node 108 to be reset to the power supply voltage VDD (reset level).
In the next period T2, the gate driving signal φR(m) goes Low level, causing the reset transistor 131 to turn OFF. Meanwhile, since the gate driving signal φS(m) applied to the select transistor 133 goes High level, the reset level is read to the vertical signal line 135 via the amplification transistor 132 and the ON-state select transistor 133. In this case, the amplification transistor 132 and the constant-current load transistor 134 constitute a source follower circuit.
In the next period T3, the gate driving signal φS(m) goes Low level, causing the select transistor 133 to turn OFF. Meanwhile, since a gate driving signal φT(m, 1) applied to the transfer transistor 102 of the 1st line of the m-th row goes High level, the potential under the gate becomes deeper, so that the signal charge (electrons) stored in the photodiode 101 the 1st line of the m-th row is transferred to the charge detection node 108.
In the next period T4, the gate driving signal φT(m, 1) goes Low level, causing the transfer transistor 102 of the 1st line of the m-th row to turn OFF, while the charge detection node 108 is held at the voltage of the signal charge transfer. Meanwhile, because the gate driving signal φS(m) goes High level, a signal level of the m-th row is read to the vertical signal line 135 via the amplification transistor 132 and the ON-state select transistor 133.
After one horizontal scan period (1H period), for the pixel of the 2nd line of the m-th row, signal charge derived from the photodiode 101 of the 2nd line of the m-th row is led to the reset transistor 131, the amplification transistor 132 and the select transistor 133 via the transfer transistor 102 of the 2nd line of the m-th row. Then, operations similar to those of the foregoing T1 to T4 are performed.
In this proposed amplification type solid-state image pickup device, for example, an assumption that one common part (i.e., charge detection node 108, reset transistor 131, amplification transistor 132 and select transistor 133) is given for each two pixels is equivalent to 2.5 transistors per pixel. Also, one common part provided for each four pixels is equivalent to 1.75 transistors per pixel. Therefore, the number of transistors per pixel is reduced, as compared with a general APS image sensor comprising three to four MOS transistors per pixel.
However, with the technique of JP H09-46596A, there would arise problems as shown below. That is, given that the capacitance of the common charge detection node 108 is CFD, a charge-voltage conversion efficiency η at which signal charge Qsig derived from the photodiode 101 is converted to a voltage signal Vsig isη=G·Vsig/Qsig=G/CFD where G is the gain of the source follower circuit made up of the amplification transistor 132 and the constant-current load transistor 134, being generally smaller than 1.
As apparent from this equation, the capacitance CFD needs to be reduced in order to increase the charge-voltage conversion efficiency η. The capacitance CFD of the common charge detection node 108 is a total sum of drain-side junction capacitances of a plurality of transfer transistors 102 connected to the charge detection node 108, a gate capacitance of the amplification transistor 132, and a node-side junction capacitance of the reset transistor 131. Therefore, the capacitance CFD increases with increasing number of pixels (photodiodes 101 and transfer transistors 102) connected to a common charge detection node 108, which leads to a problem that the charge-voltage conversion efficiency η decreases.